Workshop 2005 main topic

  53 attendees were involved in the 5th Eufanet workshop in Arcachon (France) on Wednesday, October 12, 2005. The hot topic this year was "Diagnostic ATPG and CAD approaches for IC analysis”. To achieve efficient fault localisation, it is necessary to couple information from layout, test and simulation with diagnostic tools (e.g. light emission). The challenge presented during this Eufanet meeting is to link the three worlds of design, test and failure analysis : Design can give localisation of suspected blocks. Test can highlights electrically failed nodes. While diagnostic tool may give a physical localization, such as light emission spots. Combining efficiently these information is becoming a key issue for the success of IC analysis.

Workshop 2005 content

  Welcome, introduction and EUFANET status update - Philippe Perdu (EUFANET_Program_2005pp.pdf)

  Standard ATPG analysis flow used at Infineon and statistical Scan Test Analysis (SSTA) for analysis purposes (Markus Gruetzner, Infineon)

  Truth table analysis (Stéphanie Allemand, ST Grenoble) (Cancelled)

  Knights CAD Navigation, Review and New developments (Michael Bruegel, Knights)

  FA-Navigation (Kume Toshihiro, Hamamatsu)

  Bringing Closer the Logical and Physical Worlds for Device Analysis - Roger Nicholson, Credence(NVIDIA.chip.powerpoint1.pdf)

  Debate on Diagnostic ATPG and CAD approaches for IC analysis (Eufanet Esref2005 summary.pdf)