Workshop Program

Monday, November 28th

Welcome - Introduction

Tutorial

“System in Package – how to cope with increasing challenges?”, W. Mack, Infineon

2 - Manufacturing

2-1 “Stacking of Known Good Rebuilt Wafer without TSV Applications to heterogeneous System in Package”, C. Val, 3D+

2-2 “Wafer-bond micro-void physical analysis”, C. Cassidy, AMS

Coffee break

2-3 “Low profile Silicon interposer using Passive Integration (PICS)”, S. Bellenger, IPDIA

2-4 “3D Integration developments & manufacturing offer @ CEA-LETI”, D. Henry, CEA/LETI

Lunch

3 - Reliability Test

3-1 “Reliability challenges of 3D stacked Ics”, K. Croes IMEC

3-2 “Reliability of TSV interconnects in 3D-IC Electromigration voiding analysed through 3D-FIB-SEM”, T. Frank, STM

3-3 “Sample preparation, tests and coupling of experimental and simulation results for the extraction of reliability's parameters of an interface of packages”. X. Chauffleur, Insidix / Epsilon

3-4 “Wear out Analysis in Vertical DMOS Under Repetitive Short Circuit Testing”, J. Rhayem, ON Semiconductor

Coffee break

4 - Non destructive techniques (I)

4-1 “Application of Micro CT for Non Destructive FA”, M. Cason, ST

4-2 “Failure analysis with X-ray micro computed tomography: state-of-the-art, limitations and future developments”, P. Shutz EMPA

4-3 “Contactless high resolution characterization of 3D current path in advanced SIP packages”, F. Infante Intraspec

4-4 “3D Current Path in Stacked Devices”, K. Kor, NTU

Coffee break

5 - Non destructive techniques (II)

5-1 “Advanced techniques for non destructive characterization of MEMS devices and packaging – case studies”, J. Dhennin, Novamems

5-2 “Improved Inspection of Miniaturised Interconnections by Digital X-ray Inspection and Computed Tomography”, J. Lübbehüsen, GE

5-3 “Novel Non-Destructive Characterization of Metal to Metal Bonding Interface Methodology for 3D-IC”, R. I Made, NTU

5-4 “New methodology to characterize packaging with acoustic microscopy”, Y. Ousten, IMS

Wrap-up day 1

Buffet

Tuesday, November 29th

Welcome - Introduction

6 - Electrical Test and Localization (I)

6-1 “3D Defect localization on System in Packages using Lock-in Thermographie”, Ch. Schmidt, IWMH

6-2 “Extension of Lock in thermography for thermal conductivity characterization and localisation of defects in depth”, A. Porcher, Epsilon

6-3 “Use of Lock-In Thermography for non-destructive 3D Defect Localization on System in Package and Stacked-Die Technology”, A. Reverdy Sector

6-4 “3D Localization by Lock-in Thermography”, A. Loubaresse, STEricsson

Coffee, Poster & Discussion Corner

Lunch

7 - Electrical Test and Localization (II)

7-1 “Electrical test challenges for 3D”, E.J. Marinissen, IMEC

7-2 “SAM failure analysis using scanning acoustic microscopy for diagnostics of electronic devices and 3D system integration technologies”, P. Czurratis, Tepla PVA AS

7-3 “Current Induced Failure Analysis of Ni-based Microinsert Interconnections for Flip Chip Die on Wafer Attachment.”, D. Arias Sector/CEA-Leti

Coffee break

8 - Sample Preparation and Failure Analysis

8-1 “3D failures: Identify and meet the challenge of the third axis”, S. Lavagne, Thales

8-2 “Failure Analysis for eWLB-Packages - Strategy, Fail Mechanisms”, F. Felux, Infineon

8-3 “High throughput cross sectioning by plasma FIB and combined laser ablation”, L. Kwakman, FEI

8-4 “3D IC Chip access“, M. Lefevre, Digit Concept

Wrap-up day 2

Lab Tour CNES

Many thanks to our buffet sponsors, please visit their website: