Automated PICA transistor channeling & spatial-temporal photon correlation for faster IC diagnostics, by R.Desplats/F.Beaudoin/G.Gaggion/O.Jesson/P.Perdu, CNES - French Space Agency. M.Leibowitz/T.Lundquist/K.Shah, NPTest, Inc. from NPTest, Technology Library, IRPS 2003 presented paper.

Acoustic microscopy, C-Mode Scanning, IBM. The information on Applications, Technique, Instrument Model and Sample are included.

A New Photon Detector for Device Analysis: Superconducting Single Photon Detector Based on a Hot Electron Effect, by S. Somani, S. Kasapi, K. Wilsher, W. Lo, R. Sobolewski, G. Gol'tsman, JVSTB, 2001.

Application of Near IR, Phase Contrast Imaging to Backside Failure Isolation and Analysis,  by R. Aaron Falk, Edward W. Budiarto, from International Symposium for Testing and Failure Analysis (ISTFA).

Backside Thermal Mapping Using Active Laser Probe, by R. Aaron Falk. This article appeared in Electronic Device Failure Analysis News, May 2000. The transition to “flip-chip” packaging has forced a renaissance in innovative failure analysis methods, usually referred to as backside failure analysis. This article describes one such technique, based on active laser probing.

Backside Emission Microscopy Pinpoints Wafer Level Defets.

Backside Inspection. When the traditional methods of locating defects with emission microscopes are inadequate, backside inspection are needed. Light emissionscan be detected from the back side of chip if some rear silicon is removed first. Tom Adams analyses technology which has made back side inspection feasible.

Backside Package Device Preparation and Inspection., Ceramic, Plastic, Flip Chip and BGA Techniques for Analysis, (Power Point Presentations), from Hypervision Inc.

Consistency of optical data from PICA, by T.Lundquist/K.Shah/A.Abraham, NPTest, Inc. W.Ng, National Semiconductor Corp. IRPS 2003.

Coaxial, Photon-Ion Technology Enables Direct Navigation to Buried Nodes on Planarized Surfaces, including Silicon, by M.A. Thompson, C. Richardson, E. LeRoy, T. Lundquist, W.B. Thompson, ISTFA 2002.

Current leakage fault localization using backside OBIRCH, by Beaudoin, F. Imbert, G.   Perdu, P.   Trocque, C., THALES Lab., CNES, Toulouse. In this paper, a backside failure analysis case study on four-level interconnection BICMOS ICs is presented.

Comparison of Laser and Emission Based Optical Probe Techniques, by W. Lo, S. Kasapi, and K. Wilsher.

Characterize Gate-Level Transistor Performance with PICA, by Ted Lundquist and Moyra McManus, Semiconductor International.

Diagnosis and Characterization of Timing-Related Defects by Time-Dependent Light Emission, by  Dan Knebel, Pia Sanda, Moyra Mc Manus, J. A. Kash, J. C., Tsang, Dave Vallett, Leendert Huisman, Phil Nigh, Rick Rizzolo, Peilin Song, Franco Motika. Presented at ITC 1998.

Diagnosing Latch-up with Backside Emission Microscopy, by Thomas Kessler, Friedrich-Wilhelm Wulfert, Thomas Adams, from Hypervision Inc, technical library.

Designed-in-Diagnostics: A New Optical Method, by K.Wilsher. from NPTest, Technology Library, ITC 2003 presented paper.

Diagnosis and Characterization of Timing-Related Defects by Time-Dependent Light Emission, by Dan Knebel, Pia Sanda, Dave Vallett, Leendert Huisman, Rick Rizzolo, Peilin Song, etc. In this paper, a new method of circuit characterization, using light pulses emitted during circuit switching, is described. A diagnosis example of a timing failure caused by a resistive path to a single transistor is described.

Defect Localization – Fault Isolation, Mechanical Probing, IBM. The applications include: DC Probing of wafers and single or packaged die; Active probing of packaged die; Liquid crystal analysis of wafers; Elevated and low temperature probing.

Effects of Ga Staining due to FIB Editing on IR Imaging of Flip Chips , by Q.S. Wang, C-C. Tsao, J. Fernandez, E. Delenia, T. Lundquist.

Emission Microscopes Reveal IC Defects. Fault Localization Using Time-Resolved Photon Emission and STIL Waveforms, by K.Wilsher. from NPTest, Technology Library, ITC 2003 presented paper.

Failure analysis from the back side of a die , By Liebert, S. Philips Semicond., Zurich; Authors developed a failure analysis flow which contains back side and front side failure analysis methods, consisting of back side photoemission microscopy after bulk Si thinning and electrical recontacting of the die for electrical defect localization.

Failure Analysis of Timing and IDDq-only Failures, from the SEMATECH Test Methods Experiment, by Phil Nigh, Dave Vallett, Atul Patel, Jason Wright. This paper presents the results of the failure analysis portion of a project. The testing, reliability stressing, characterization, fault diagnosis and physical analysis results are presented for 25 devices including “IDDq-only” failures and “delay test-only” failures.

Fault Localization using Time Resolved Photon Emission and STIL waveforms, by Romain Desplats, Felix Beaudoin, Philippe Perdu, Nagamani Nataraj, Ted Lundquist, Ketan Shah. Faster defect localization is achieved by combining IC simulations and internal measurements. Time resolved photon emission records photons emitted during commutations (current) rather than determining the voltage states. Comparing measured waveforms with simulations (STIL/VCD) localizes functional faults and timing issues.

Hypervision Backside-Thinned Emission Imaging of Packages Devices and Wafers, from Asian Electronics Engineer. Emission microscopy uses the emit light defected by the chip to find the exact location of a defect on a chip. Emission microscopes make two separate images. One is the image of the defect, which is made by greatly amplifying the licht from the defect. The other is the image of the structure of the chip, which is made by illuminating the chip. The location of the defect can be found after overlay these two images.

IC Fault Location Motorola & QFI 2002, By S. Kiefer, M. Nair, P. Sanders, J. Steele, M. Sutton, R. Thoma, S. Wilson, Albright, C. Li, J. MacDonald, from Quantum Focus Instruments Corporation.  In order to understand spatial and temperature resolution limits of an infrared microscope used for fault location in semiconductor devices, numerical models and bench methods are correlated and discussed. Results clearly show fault identification capability in the sub-micron realm and “hot-spot” resolution of a few tenths of a degree K.

LSI Failure Analysis Using Focused Laser Beam Heating, by Kiyoshi NIKAWA and Shoji INOUE, NEC, 22-28020, 1753 Shimo-numabe Nakahara-ku Kawasaki 211 JAPAN, TDI. In this paper, authors present the recent new results about three methods, and discuss on advantages and disadvantages of these applications over other methods.

Laser-Induced Debug and Failure Analysis, by Praveen Vedagarbha, Gary Woods, Hiroyasu Koike and Kevin Sanchez. A laser is used to measure timing and frequency shifts and to induce pass/fail behavior in a circuit with a controllable race condition.

Methods of using measured time resolved photon emission data and simulated time resolved photon emission data for fault localization, by Romain Desplats, Philippe Perdu, Ketan Shah, Martin Leibowitz, Theodore R. Lundquist. Fault localization methods, using measured time resolved photon emission data and simulated time resolved photon emission data, are provided and described in this paper.

MERCAD Emission Microscopy (Recombination and Heat Detection) and TIVA, by Neeraj Khurana, MERCAD Emission Microscopy system can detect both Photoemission and Ohmic Defects with extreme sensitivity. Such a system should be the primary failure analysis tool prior to Laser Injection because the MERCAD system detects most defects in a totally non-destructive fashion.

Next-Generation Optical Probing Tools for Design Debug of High Speed Integrated Circuits, W. Lo, K. Wilsher, R. Malinsky, N. Boiadjieva, CC. Tsao, M. Leibowitz, and H. Deslandes ISTFA 2002.

Next-Generation optical probing tools for design debug of microprocessor integrated circuits, by W. Lo, S. Kasapi, and K. Wilsher IEEE LEOS Newsletter, December 2001.

Optical and Electro-Optical FA Microscopy, by John McDonald, microscopy tutorial. Quantum Focus Instruments Corporation, QFI.

Practical, Non-invasive Optical Probing for Flip-Chip Devices, by G. Dajee, N. Goldblatt, T. Lundquist, S. Kasapi, K. Wilsher.

PICA Watches Chips Work, by Moyra McManus and Steven Kasapi, Optoelectronics World 07/2000.

Seeing Through the back door, by D. HURLEY of Hypervision, M. MAHANPOUR, M. MASSOODI of AMD. Advancement in microelectronic devices occurs as  manufacturing techniques allow more activity in a smaller space. This ensures a greater density of material in a tiny area. As there is an increase in density there is a parallel increase in inspection difficulty. Look at the new techniques that can detect metallisation defects through the backside of  devices.

Spatial and temporal selective laser assisted fault localization, by  Philippe Perdu, Romain Desplats, Felix Beaudoin, Praveen Vedagarbha, Martin Leibowitz, Kenneth R. Wilsher. from FreshPatents.com. In this paper, authors provide the method and apparatus for laser-assisted fault mapping which synchronizes the laser control with the tester unit.

Space Microelectronics Failure Analysis: Problem Interconnect Issues qnd Advanced Interconnect Defect Localization, by Jerry M. Soden and Edward I. Cole Jr. Sandia National Laboratories,  Albuquerque, NM. The purpose is to describe failure analysis issues for resolving spade microelectronics problems and advanced techniques for localizating interconnection defects. SEM (electron beam) and SOM (photon beam)  techniques are talked.

S/390 G5 CMOS microprocessor diagnostics, by P. Song, F. Motika, D. R. Knebel, R. F. Rizzolo, and M. P. Kusko. This paper describes the strategies and techniques used to diagnose failures in the IBM 600-MHz S/390^® G5 (Generation 5) CMOS microprocessor and the associated cache chips. Beginning with the first prototype of the G5 microprocessor chip, intense chip diagnostics and physical failure analysis (PFA) have successfully identified the root causes of many failures, including process, design, and random manufacturing defects. In this paper, three different diagnostic techniques are described that have enabled the G5 to achieve its objective.

Sub-resolution placement using IR image to CAD database aligment: an algorithm for silicon-side probing, by M. Sengupta, L. Johri, C-C. Tsao, M. Thompson, T. Lundquist, SPIE Imaging 2002.

Unique and Practical IC Timing Analysis Tool Utilizing Intrinsic Photon Emission, by Norman Goldblatt, Martin Leibowitz and William Lo, Published Paper from ESREF, October 2001.

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